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M48Z129Y M48Z129V
3.3V/5V 1 Mbit (128Kb x8) ZEROPOWER(R) SRAM
s
INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY AUTOMATIC POWER-FAIL CHIP DESELECT AND WRITE PROTECTION MICROPROCESSOR POWER-ON RESET (RESET VALID EVEN DURING BATTERY BACK-UP MODE) BATTERY LOW PIN - PROVIDES WARNING OF BATTERY END-OF-LIFE WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48Z129Y: 4.2V VPFD 4.5V - M48Z129V: 2.7V VPFD 3.0V CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS OF DATA RETENTION IN THE ABSENCE OF POWER PIN AND FUNCTION COMPATIBLE WITH JEDEC STANDARD 128Kb x 8 SRAMS SELF CONTAINED BATTERY IN DIP PACKAGE
17 A0-A16 W E G
G W RST BL VCC VSS Output Enable Write Enable Reset Output (Open Drain) Battery Low Output (Open Drain) Supply Voltage Ground
32 1
s
s
s
s
PMDIP32 (PM) Module
s
Figure 1. Logic Diagram
s
s
s
VCC
8 DQ0-DQ7 M48Z129Y M48Z129V RST BL
Table 1. Signal Names
A0-A16 DQ0-DQ7 E Address Inputs Data Inputs / Outputs Chip Enable
VSS
AI02309
June 2000
1/13
M48Z129Y, M48Z129V
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG Parameter Ambient Operating Temperature Storage Temperature (VCC Off) Value 0 to 70 -40 to 70 -10 to 70 260 -0.3 to VCC+0.3 M48Z129Y M48Z129V -0.3 to 7.0 -0.3 to 4.6 Unit C C C C V V
TBIAS
TSLD (2) VIO VCC
Temperature Under Bias
Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode.
Figure 2A. DIP Pin Connections
RST A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
32 1 31 2 30 3 29 4 28 5 27 6 26 7 8 M48Z129Y 25 9 M48Z129V 24 23 10 22 11 21 12 20 13 19 14 18 15 17 16
AI02310
VCC A15 BL W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
128K x 8 SRAM. It also provides the non-volatility of FLASH without any requirement for special write timing or limitations on the number of writes that can be performed. The M48Z129Y/V also has its own Power-Fail Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When V CC is out of tolerance, the circuit write protects the SRAM, providing data security in the midst of unpredictable system operation. As VCC falls, the control circuitry automatically switches to the battery, maintaining data until valid power is restored. READ MODE The M48Z129Y/V is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable) is low. The unique address specified by the 17 Address Inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within tAVQV (Address Access Time) after the last address input signal is stable, providing the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access Times (tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before t AVQV, the data lines will be driven to an indeterminate state until t AVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for tAXQX (Output Data Hold Time) but will go indeterminate until the next Address Access.
DESCRIPTION The M48Z129Y/V ZEROPOWER SRAM is a 1,048,576 bit non-volatile static RAM organized as 131,072 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM and a control circuit in a plastic 32 pin DIP Module. The M48Z129Y/V directly replaces industry standard
2/13
M48Z129Y, M48Z129V
Table 3. Operating Modes (1)
Mode Deselect Write Read Read Deselect Deselect VCC 4.5V to 5.5V (M48Z129Y) or 3.0V to 3.6V (M48Z129V) VSO to VPFD (min) (2) VSO (2) E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS Standby Battery Back-up Mode
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 2. See Table 7 for details.
Figure 3. Block Diagram
VCC
A0-A16
POWER E VOLTAGE SENSE AND SWITCHING CIRCUITRY
131,072 x 8 SRAM ARRAY
DQ0-DQ7
E
W G
INTERNAL BATTERY
RST
BL
VSS
AI03608
WRITE MODE The M48Z129Y/V is in the Write Mode whenever W (Write Enable) and E (Chip Enable) are active. The start of a write is referenced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from Write Enable prior to the initiation of another read or write cycle. Data-in must be valid tDVWH prior to the end of write and remain valid for tWHDX afterward. G should be kept high during write cycles to avoid
bus contention; although, if the output bus has been activated by a low on E and G a low on W will disable the outputs t WLQZ after W falls. DATA RETENTION MODE With valid V CC applied, the M48Z129Y/V operates as a conventional BYTEWIDE static RAM. Should the supply voltage decay, the RAM will automatically deselect, write protecting itself when V CC falls between VPFD (max), VPFD (min) window. All outputs become high impedance and all inputs are treated as "don't care".
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M48Z129Y, M48Z129V
Table 4. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 5ns 0 to 3V 1.5V
DEVICE UNDER TEST 650
Figure 4. AC Testing Load Circuit
Note that Output Hi-Z is defined as the point where data is no longer driven.
Note: A power failure during a write cycle may corrupt data at the current addressed location, but does not jeopardize the rest of the RAM's content. At voltages below V PFD(min), the memory will be in a write protected state, provided the V CC fall time is not less than t F. The M48Z129Y/V may respond to transient noise spikes on VCC that cross into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When V CC drops below VSO, the control circuit switches power to the internal battery, preserving data. The internal energy source will maintain data in the M48Z129Y/V for an accumulated period of at least 10 years at room temperature. As system power rises above V SO, the battery is disconnected, and the power supply is switched to external VCC. Deselect continues for tREC after VCC reaches V PFD(max). For more information on Battery Storage Life refer to the Application Note AN1012. POWER-ON RESET OUTPUT All microprocessors have a reset input which forces them to a known state when starting. The M48Z129Y/V has a reset output (RST) pin which is guaranteed to be low below VPFD(min). This signal is an open drain configuration. An appropriate pull-up resistor should be chosen to control the rise time. This signal will be valid for all voltage conditions, even when VCC equals VSS. Once VCC exceeds the power failure detect voltage VPFD, an internal timer keeps RST low for tREC to allow the power supply to stabilize. BATTERY LOW PIN The M48Z129Y/V automatically performs battery voltage monitoring upon power-up, and at factory-
CL = 100pF or 50pF(1)
1.75V
CL includes JIG capacitance
AI03630
Note: 1. 50pF for M48Z129V (3.3V).
programmed time intervals of 24 hours. The Battery Low (BL) pin will be asserted if the battery voltage is found to be less than approximately 2.5V. If a battery low is generated during a power-up sequence, this indicates that the battery is below 2.5 volts and may not be able to maintain data integrity in the SRAM. Data should be considered suspect, and verified as correct. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal V CC is supplied. The M48Z129Y/V only monitors the battery when a nominal V CC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. The BL pin is an open drain output and an appropriate pull-up resistor should be chosen to control the rise time.
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M48Z129Y, M48Z129V
Table 5. Capacitance (1) (TA = 25 C, f = 1 MHz)
Symbol CIN CIO (2) Parameter Input Capacitance Input / Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 10 10 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 5V. 2. Outputs deselected.
Table 6A. DC Characteristics (TA = 0 to 70 C; VCC = 4.5V to 5.5V)
Symbol ILI (1) ILO (1) ICC ICC1 ICC2 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1mA IOH = -1mA 2.4 Test Condition 0V VIN VCC 0V VOUT VCC Outputs open E = VIH E = VCC - 0.2V -0.3 2.2 Min Max 1 1 95 7 4 0.8 VCC + 0.3 0.4 Unit A A mA mA mA V V V V
Note: 1. Outputs deselected.
Table 6B. DC Characteristics (TA = 0 to 70 C; VCC = 3.0V to 3.6V)
Symbol ILI (1) ILO (1) ICC ICC1 ICC2 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1mA IOH = -1mA 2.2 Test Condition 0V VIN VCC 0V VOUT VCC Outputs open E = VIH E = VCC - 0.2V -0.3 2.2 Min Max 1 1 50 4 3 0.6 VCC + 0.3 0.4 Unit A A mA mA mA V V V V
Note: 1. Outputs deselected.
5/13
M48Z129Y, M48Z129V
Table 7. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70 C)
Symbol VPFD Parameter Power-fail Deselect Voltage (M48Z129Y) Power-fail Deselect Voltage (M48Z129V) Battery Back-up Switchover Voltage (M48Z129Y) Battery Back-up Switchover Voltage (M48Z129V) Expected Data Retention Time 10 Min 4.2 2.7 Typ 4.35 2.9 3.0 V 2.45 YEARS Max 4.5 V 3.0 Unit
VSO tDR (2)
Note: 1. All voltages referenced to VSS. 2. At 25 C.
Table 8. Power Down/Up AC Characteristics (TA = 0 to 70 C)
Symbol tF (1) tFB (2) tR tRB tWPT tREC Parameter VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSS VCC Fall Time (M48Z129Y) VPFD (min) to VSS VCC Fall Time (M48Z129V) VPFD (min) to VPFD (max) VCC Rise Time VSS to VPFD (min) VCC Rise Time Write Protect Time (M48Z129Y) Write Protect Time (M48Z129V) VPFD (max) to RST High Min 300 10 s 150 10 1 40 40 40 150 s 250 200 ms s s Max Unit s
Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes V PFD (min). 2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
6/13
M48Z129Y, M48Z129V
Figure 5. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tWPT E
RECOGNIZED
tR tRB tREC
DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
RST
AI03610
Table 9. Read Mode AC Characteristics (TA = 0 to 70 C; VCC = 4.5V to 5.5V or 3.0V to 3.6V)
M48Z129Y Symbol Parameter Min tAVAV tAVQV (1) tELQV (1) tGLQV (1) tELQX (2) tGLQX (2) tEHQZ (2) tGHQZ (2) tAXQX (1) Read Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition 5 5 3 30 20 5 70 70 70 35 5 5 40 25 -70 Max Min 85 85 85 45 M48Z129V -85 Max ns ns ns ns ns ns ns ns ns Unit
Note: 1. CL = 100pF or 50pF (see Figure 4). 2. CL = 5pF (see Figure 4).
7/13
M48Z129Y, M48Z129V
Figure 6. Address Controlled, Read Mode AC Waveforms.
tAVAV A0-A16 tAVQV tAXQX DQ0-DQ7 DATA VALID DATA VALID VALID
AI02324
Note: Chip Enable (E) and Output Enable (G) = Low, Write Enable (W) = High.
Figure 7. Chip Enable or Output Enable Controlled, Read Mode AC Waveform
tAVAV A0-A16 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 DATA OUT
AI01197
VALID tAXQX tEHQZ
tGHQZ
8/13
M48Z129Y, M48Z129V
Table 10. Write Mode AC Characteristics (TA = 0 to 70 C; VCC = 4.5V to 5.5V or 3.0V to 3.6V)
M48Z129Y Symbol Parameter Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ (1, 2) tAVWH tAVEH tWHQX (1, 2) Write Cycle Time Address Valid to Write Enable Low Address Valid to Chip Enable Low Write Enable Pulse Width Chip Enable Low to Chip Enable High Write Enable High to Address Transition Chip Enable High to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable Low to Output Hi-Z Address Valid to Write Enable High Address Valid to Chip Enable High Write Enable High to Output Transition 65 65 5 70 0 0 55 55 5 15 30 30 0 10 25 75 75 5 -70 Max Min 85 0 0 65 75 5 15 35 35 0 15 30 M48Z129V -85 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. CL = 5pF (see Figure 4). 2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Figure 8. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A16 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI02382
tWHAX
tWHQX
9/13
M48Z129Y, M48Z129V
Figure 9. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A16 VALID tAVWH tAVEL E tWLWH tAVWL W tELEH tEHAX
tDVWH DQ0-DQ7 DATA INPUT
tWHDX
AI03611
Figure 10. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
POWER SUPPLY DECOUPLING AND UNDERSHOOT PROTECTION Icc transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the V CC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 microfarad is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V CC that drive it to values below Vss by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to Vss (cathode connected to VCC, anode to Vss). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount).
10/13
M48Z129Y, M48Z129V
Table 11. Ordering Information Scheme
Example: Supply Voltage and Write Protect Voltage 129Y = VCC = 4.5V to 5.5V; VPFD = 4.2V to 4.5V 129V = VCC = 3.0V to 3.6V; VPFD = 2.7V to 3.0V Speed -70 = 70ns (M48Z129Y) -85 = 85ns (M48Z129V) Package PM = PMDIP32 Temperature Range 1 = 0 to 70 C M48Z129Y -70 PM 1
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. Table 12. Revision History
Date December 1999 03/30/00 06/20/00 First Issue From Preliminary Data to Data Sheet tGLQX changed for M48Z129Y (Table 9) Revision Details
11/13
M48Z129Y, M48Z129V
Table 13. PMDIP32 - 32 pin Plastic Module DIP, Package Mechanical Data
mm Symb Typ A A1 B C D E e1 e3 eA L S N Min 9.27 0.38 0.43 0.20 42.42 18.03 2.29 34.29 14.99 3.05 1.91 32 Max 9.52 - 0.59 0.33 43.18 18.80 2.79 41.91 16.00 3.81 2.79 Typ Min 0.365 0.015 0.017 0.008 1.670 0.710 0.090 1.350 0.590 0.120 0.075 32 Max 0.375 - 0.023 0.013 1.700 0.740 0.110 1.650 0.630 0.150 0.110 inches
Figure 11. PMDIP32 - 32 pin Plastic Module DIP, Package Outline
A
A1 S B e3 D e1
L eA
C
N
E
1 PMDIP
Drawing is not to scale.
12/13
M48Z129Y, M48Z129V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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